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Sparse matrix operations on several multi-core architectures

  • Carsten Trinitis
    ,
  • Tilman Küstner
    ,
  • Josef Weidendorfer
    ,
  • Jasmin Smajic
Research Output:
Contribution to journal
Article
 Peer-review

Abstract

This paper compares various contemporary multicore-based microprocessor architectures from different vendors with different memory interconnects regarding performance, speedup, and parallel efficiency. Sparse matrix decomposition is used as a benchmark application. The example matrix used in the experiments comes from an electrical engineering application, where numerical simulation of physical processes plays an important role in the design of industrial products. Within this context, thread-to-core pinning and cache optimization are two important aspects which are investigated in more detail.

Publication Information

Output type

Research Output:
Contribution to journal
Article
 Peer-review

Original language

English

Pages from-to (Number of pages)

Pages 132-140

Journal (Volume, Issue Number)

Journal of Supercomputing (Volume 57)

Publication milestones

  • Published - 01/01/2010

Publication status

Published - 01/01/2010

ISSN

0920-8542

Publication IDs

  • handle.net: 10547/250939
  • Scopus: 80051544023

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