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Low latency parallel turbo decoding implementation for future terrestrial broadcasting systems

  • Hua Luo
    ,
  • Yue Zhang
    ,
  • Wei Li
    ,
  • Li-Ke Huang
    ,
  • John Cosmas
    ,
  • Dayou Li
Research Output: Contribution to journal Article Peer-review

Open access

Abstract

As a class of high-performance forward error correction codes, turbo codes, which can approach the channel capacity, could become a candidate of the coding methods in future terrestrial broadcasting (TB) systems. Among all the demands of future TB system, high throughput and low latency are two basic requirements that need to be met. Parallel turbo decoding is a very effective method to reduce the latency and improve the throughput in the decoding stage. In this paper, a parallel turbo decoder is designed and implemented in field-programmable gate array (FPGA). A reverse address generator is proposed to reduce the complexity of interleaver and also the iteration time. A practical method of modulo operation is realized in FPGA which can save computing resources compared with using division operation. The latency of parallel turbo decoder after implementation can be as low as 23.2 us at a clock rate of 250 MHz and the throughput can reach up to 6.92 Gbps.

Publication Information

Output type

Research Output: Contribution to journal Article Peer-review

Original language

English

Pages from-to (Number of pages)

Pages 96-104

Journal (Volume, Issue Number)

IEEE Transactions on Broadcasting (Volume 64, Issue 1)

Publication milestones

  • Published - 21/06/2017

Publication status

Published - 21/06/2017

ISSN

0018-9316

External Publication IDs

  • handle.net: 10547/623814
  • Scopus: 85021790932

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