Design of energy-efficient approximate arithmetic circuits for error tolerant medical image processing applications

Medical image processing encompasses the use and investigation of human body image collections, usually from a Computed Tomography (CT) to diagnose pathologies for disease detection. Energy efficiency is one of the key parameters in the design of very large-scale integrated circuits. For more power consuming circuits, the traditional methodologies deal with limited approaches. In recent years, approximate computing techniques improve the design metrics power, delay, and area with a limitation on accuracy. High performance computing and Error tolerant applications are preferred to implement Approximation techniques. Many multimedia applications, such as digital image and video processing, can introduce minor errors in the processed output. For these applications, approximate computational approach offers good performance in terms of low power consumption at a trade-off of accuracy. This is best suited for arithmetic circuits. Several improved versions of Approximate adders (PAA_s) and Approximate Subtractors (APSC8-APSC10) have been proposed in this paper for basic operations. Based on these designs, multipliers and dividers have developed and also performance is compared with previous designs. The proposed designs achieve a better peak signal-to-noise ratio (PSNR).